1. Field of the Invention
The present invention relates to a read method, and more particularly, to a read method for multiple-value memory cells in a semiconductor memory such as a nonvolatile semiconductor memory.
2. Description of the Prior Art
In recent years, because of the increasing demand for memory, a new type of memory, which is a so called multiple-value memory, was developed to meet the demand.
The multiple-value memory technique is based on nonvolatile semiconductor memory. A multiple-value memory uses a nonvolatile memory cell having a control gate and a floating gate as a memory cell. It is possible to constitute the memory cell out of one transistor. Please refer to FIG. 1, which is a conceptual method for storing information comprising a plurality of bits in and reading the stored information from a transistor 100. Data are stored in the transistor 100 as its thresholds. When the stored data is read, first the bit line 120 is pre-charged to 1V and the conjugate bit line 130 is pre-charged to 0.5V. Second, the word line 140 is turned on. If the threshold of the transistor 100 is higher than the voltage of the word line 140, the voltage of the bit line 120 is still 1V. If the threshold of the transistor 100 is lower than the voltage of the word line 140, the voltage of the bit line 120 is discharged to ground. Then the sense amplifier 110 is activated to compare the voltages of the bit line 120 and the conjugate bit line 130. If the voltage of the bit line 120 is ground voltage while the voltage of the conjugate bit line 130 is 0.5V, the sense amplifier outputs “0”. And if the voltage of the bit line 120 is 1V while the voltage of the conjugate bit line 130 is 0.5V, the sense amplifier outputs “1”.
When storing information into the transistor 100, stepwise changing of thresholds to 1V, 2V, 3V, . . . , can make one bit of information of a plurality of bits correspond to each threshold value. FIG. 2 shows a threshold value distribution state when storing information by dividing one memory cell into four threshold value states. It is difficult to accurately control the threshold value of a memory cell to a predetermined value for a write operation, and therefore, as shown in FIG. 2, a normal distribution is established around each target threshold voltage. To read data, voltages corresponding to the valleys of the threshold value distributions are read, set as VRW1, VRW2, and VRW3, and applied to a control gate through a word line. For example, please go back to refer to FIG. 1, if the threshold of the transistor 100 falls in the threshold value distribution B, when voltage VRW3 is applied to the word line 140, the sense amplifier 110 is “0”. If voltage VRW2 is applied to the word line 140, the sense amplifier 110 is “1”. When voltage VRW1 is applied to the word line 140, the sense amplifier 110 is “1”. Please refer to FIG. 3. As the example described above, FIG. 3 shows the results of reading data at the sense amplifier 110 from memory cells belonging to the threshold value distributions A, B, C, D by using the above read voltages VRW1, VRW2, and VRW3 (VRW1<VRW2<VRW3).
Please refer to FIG. 4. FIG. 4 is a diagram illustrating a conventional memory device using multiple-value cells. When reading a selected multiple-value memory cell 460 in a memory array 420, a word line 470 coupled to a control gate of the selected multiple-value memory cell 460 is charged to voltages of VRW1, VRW2, and VRW3 step by step. Then the two-bit data stored in the multiple-value memory cell 460 is transferred to a right data latch 450 and a left data latch 430 through a sense amplifier (SA) 440 coupled to the right data latch (DL) 450 and the left data latch 430 with the bit line 480. Then right data latch 450 and left data latch 430 output the transferred data to external circuits through input/output ports 410.
Please refer to FIG. 5 that is a diagram illustrating the voltage of the word line 470 of the selected multiple-value memory cell 460 of FIG. 4 in a read operation. First, the word line 470 is charged to voltage VRW1. Next the word line 470 is charged to voltage VRW2. Finally the word line 470 is charged to voltage VRW3.
Please refer to FIG. 6, which is a diagram illustrating one multiple-value memory cell unit of the memory array based on FIG. 4 in a conventional memory system. The multiple-value memory cell unit is provided with a right data latch 630, a left data latch 620, a sense amplifier 650, a bit line 680, a word line 670, a multiple-value memory cell 660, and input/output ports 610. Please refer to FIG. 7 together with FIG. 6. FIG. 7 is a flowchart of a read operation based on FIG. 6. The read steps are described in sequential order as follows:
Step 700: Start.
Step 710: Charge the word line 670 to voltage VRW1 and sense a first data stored in the multiple-value memory cell 660 using the sense amplifier 650 through the bit line 680.
Step 720: Transfer the first data stored in the sense amplifier 650 to the right data latch 630 through the bit line 680.
Step 730: Charge the word line 670 to voltage VRW2 and sense a second data stored in the multiple-value memory cell 660 using the sense amplifier 650 through the bit line 680.
Step 740: Transfer the second data stored in the sense amplifier 650 to the left data latch 620 through the bit line 680.
Step 750: Charge the word line 670 to voltage VRW3 and sense a third data stored in the multiple-value memory cell 660 using the sense amplifier 650 through the bit line 680.
Step 760: Execute a predetermined calculation of the third data in the sense amplifier and the second data in the right data latch, and save the result of data calculation in sense amplifier.
Step 770: Transfer the calculation result in sense amplifier to right data latch.
Step 775: Output the memory cell data stored in right/left data latch through input/output ports 610.
Step 780: End.
According to the prior art, the right data latch is necessary to store the first data, the left data latch is necessary to store the second data, and the sense amplifier is necessary to store the third data. The first and third data are then utilized to generate the actual lower bit information stored in 2-bits per cell memory cell, while the data stored in left data latch is the actual higher bit information of memory cell. So the actual two bits information stored in memory cell are now read out in the left and right data latch.
The first disadvantage of the conventional memory system and read operation is that each multiple-value memory cell is provided with two data latches and one sense amplifier so that it is not easy to reduce the total circuit cost. Secondly, the conventional method restricts the sequence of the voltages applied to the word line to be VRW1, VRW2, and VRW3 while the relationships between the three voltages must be VRW1<VRW2<VRW3 so that this method is not flexible.